An Efficient Baugh-Wooley Architecture for Signed &Unsigned Fast Multiplication


This paper presents an efficient implementation ofa high speed multiplier using the shift and adds method of Baugh-Wooley Multiplier. This parallel multiplier uses lesser adders and lesser iterative steps. As a result of which they occupy lesser space as compared to the serial multiplier. This is very important criteria because in the fabrication of chips and high performance system requires components which are as small as possible. Experimental results demonstrate that the proposed circuit not only improves the accurate performance but also reduces the hardware complexity and also less power consumption that is dynamic power of 15.3mW and maximum clock period of 3.912ns is required which is very efficient as compared to the reference paper.

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