Design and Simulation of Multiplier for High speed Application
This paper describes an efficient implementation of high speed multiplier at the algorithm and archite-cture level, addresses Low-Power, High Speed and Less Area multiplier design systematically from two aspects: internal efforts considering multiplier architectures and external efforts considering input data characteristics. We can achieved High through-put rate by a new architecture implementing our earlier multiplication technique in conventional register pipelining at the bit level. The multiplier is designed by using Xilinx 14.7 for its synthesis result and Modelsim simulator is used for simulation. In this paper we present a study of Booth Multiplier for Area, Power and Speed in VLSI design of 8 bit Multipliers.