Abstract

When high-speed media or channels are used, high-speed data compression is desired. Software implementations are often not fast enough. In this paper, we present the very high speed hardware description language (VHDL) modeling enviro-nment of Lempel-Ziv-(LZW) algorithm for binary data compression to ease the description, veri-fication, simulation and hardware realization. The VHDL model defines a main block, which desc-ribe the LZW algorithm for binary data compression through a behavioral and structural description. The LZW algorithm for binary data compression comprises of two modules compressor and decom-pressor. The input of compressor is 1-bit bit stream read in according to the clock cycle. The output is an 8-bit integer stream fed into the deco-mpressor, which is an index that represents the memory location of the bit string stored in the dictionary. The output of decompressor is 1-bit bit stream. Once detecting the Particular approaches for input, output, main block and different modules, the VIIDL descriptions are run through a VHDL simulator, followed by the timing analysis for the validation, functionality and Performance of the designated model that supports the effective-ness of the model for the application.