Chip Design Sign-Off For Shrinking Technology
Abstract
In today’s IC’s competitive market place, as technology is shrinking and we are stepping into 45nm and below, IC’s complexity is increasing, die areas are also getting larger in order to incorporate the increased functionality that comes with more advanced technology. Due to shrinking design, physical verification of design such as design rule checking (DRC) and layout vs. schematic (LVS), may not give accurate result as expected due to electrical side effects inherent in nanometer process technology. Therefore, shrinking designs demand additional verification before being signed-off for manufacturing. For example, if signal integrity (SI) and other electrical effects are not controlled, a design will likely suffer front lower performance, lower yield, and even functional failure. Any chip failure after manufacturing will result in expensive mask changes and delays in getting the chip to market. Consequently, most designs today require a nanometer sign-off process, where the influence of different electrical effects on the functionality and Performance of the design are analyzed before manufacturing.
Authors
Anurag Sahai