Analysis of Low Density Parity Check Code Decoder for Low Power Applications
Abstract
Because of its enough error detecting and repairing capabilities the low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection & correction applications. Low Density Parity-Check codes have been adopted in latest wireless standards such as satellite and mobile communications since they obtain superior error-detecting and correcting capabilities. However, as technology advances, building such a decoder has always been a challenge because it necessitates specific memory size and power consumptions. In this paper, we propose an LDPC decoder design by the use of Booth Algorithm that addresses these check in this study. The architecture was synthesized on Xilinx 14.7, and the synthesis report showed that the propose architecture uses less hardware and consumes less power than the conventional architecture, resulting in a more standard outcome.
Authors
Amit Yadav , Kamal Bhatia , Sarabjeet Kaur