Design and Verification of Multiplier using carry look ahead adder
Abstract
A Multiplier using Carry Look Ahead Adders instead of full adders to implement the reduction of the bit product matrix into the two numbers that are added to make the product. Four-bit carry look Ahead adders are used in the reduction in place of individual full adders. Reduction of Nine partial products by a single carry look ahead adder (instead of 3 with a full adder) in same amount of time. This leads to fewer reduction stages than a traditional Wallace/Dadda Multiplier. One fewer stage is required for 4 by 4, 8 by 8, and 16 by 16 bit multipliers and 2 stages are saved for larger multipliers.
Authors
Kamal Bhatia , Amit Kumar Yadav, Nidhi Sharma